1. Field of the Invention
The present invention relates to creating metal gate structures, and more particularly to improving the metal gate structures using integrated metrology tools and procedures.
2. Description of the Related Art
With the exhaustion of other resolution-enhancement techniques (RETs) to further reduce the k1 factor and the un-readiness of Extreme Ultra-Violet (EUV) tools and hyper-NA (numerical aperture) fluid, double-patterning (D-P) techniques have gained momentum and looks to become the solution for next technology node. By splitting dense pitches into two separate loose pitches, DP can further extend the current toolset by up to two technology nodes. However, double patterning also brings with many difficult challenges. Overlay and critical dimension (CD) errors are closely coupled, and an overlay error can affect the CD measurement.
Scatterometry has been adopted to measure CD and profile. In D-P sequences, there are CDs and profiles for the first and second sets of procedures. For scatterometry modeling, this can increase the number of parameters in a model and the number of models used. In addition, there can be an overlay error between the two patterns, and the overlay error can create scatterometry errors. As the size of the structures decreases, the measurement problems increase. Many multiple patterning techniques are currently being use during semiconductor wafer processing to increase the number of features and/or structures within devices on a wafer. Multiple patterning techniques can include double exposure techniques, double patterning techniques, spacer techniques, mask techniques, and brute force techniques. In 2006, the International Technology Roadmap for Semiconductors roadmap was expanded to include double patterning a potential solution for 32 nm lithography. Multiple patterning techniques are viewed as some device manufacturers as bridge solutions that can be used until EUV techniques become more fully developed.